Fast-transient testing is a high noise event that can induce ESD clamp mis-triggering that results in chip function failure. End-products customers, concerned with ESD latchup, seek chips from chip-providers that provide a high electrical fast-transient specification but are reluctant to incur high cost of a printed circuit board (PCB) to solve ESD problems. Traditional attempts to overcome transient latch-up or static latch-up issues involve modification of ESD detection circuits that become more complex in design, requiring more area for a surface-type ESD clamp. FIGS. 1 and 2 illustrate the traditional RC-NMOS ESD clamp and feedback-type RC-NMOS ESD clamp. These circuits provide fast turn-on speed. However, a large chip area is allocated to R and C elements that are required to judge ESD event and normal function.
The IEC-like or transient latch-up testing impact on feedback-type RC-NMOS ESD clamp is shown in FIG. 3. The RC time constant of these circuits can induce false triggering. After Vcharge=−4V transient latch-up testing, the VDD drops and the IDD increases. This characteristic illustrates that latch-up like occurrences can happen on this ESD clamp during electrical fast-transient testing, such as transient latch-up testing IEC-like testing. Moreover, both the traditional RC-ESD clamp and feedback-type RC-NMOS ESD clamp can incur high noise damping or transient latch-up testing.
FIG. 4 is a modified RC-Clamp circuit. As in other type of RC-clamp circuits, it is the size of the clamping device that is usually large, in thousands of um width device. In a RC-Clamp circuit, the clamp device represents a high impedance to the circuit in normal operating condition or up to the clamp device trigger voltage (Vtl). The clamp device (or sometimes called ESD clamping device) in RC-clamp circuitry is an active device. The transient detection circuit controls the conduction of the active device. During an ESD event, the transient detection circuit will drive (bias the gate) of the active device and turn it on, i.e. become a low impedance acting as a discharge path in surface mode. The parasitic BJT (NPN in case of NMOS active device) can be further triggered on and provide another path, as the ESD signal pass/over the active device trigger voltage (Vtl).
RC-clamp circuit as an ESD device is a non-snapback device. However other ESD devices such as gate grounded NMOS, SCR and lateral NPN do have snapback characteristic.
The root cause inducing transient latch-up of RC-ESD clamp and false-triggering under electrical fast-transient testing is the RC elements. How to provide an ESD clamp with small size and high noise immunity such as transient latch-up, static latch-up free ESD clamp, becomes a more critical consideration in the development of high voltage technology.
An ESD snap-back device, once conducting current, will exhibit “snap-back” or negative resistance characteristics due to its structure. During normal operation, the ESD device represents a high impedance to the circuit up to the ESD device trigger voltage. During an ESD event, the trigger voltage will be exceeded and the ESD device will begin to conduct and enter a low impedance state. This point is defined on the curve, shown in FIG. 5, by the snap-back holding voltage (Vh) and snap-back holding current (Ih). To return to a non-conducting state, the current through the device must fall below the Ih and the voltage must fall below the Vh.
For the ESD device to be immune to static and transient latch-up, its snap-back holding voltage must be within the ESD protection windows, i.e., between supply rail voltage (VDD) and the core device breakdown voltage, as illustrated in FIG. 6. Static latch-up is an event that occurs when the clamp device becomes conductive due to lower snap-back holding voltage of the clamp device or fluctuation of the supply voltage rail (VDD). Transient latch-up is an event that occurs when the clamp device becomes conductive as a result of spikes, noise, or a start-up transient on the supply rail.
One general approach to overcome transient latch-up or static latch-up is to provide a non-snapback characteristic of ESD clamp, such as PMOS or lateral PNP. Such a device will impact on chip size due to low β compared to NMOS. In general, PMOS needs 2˜3 times the area compared to an NMOS device for a given ESD performance. Another approach is the use of PMOS or lateral PNP architecture to obtain a non-snapback characteristic. Such an arrangement encompasses a large size, approximately two to three times the area compared to NMOS architecture, and large on resistance (Ron). Surface mode PMOS with transient latch-up free ESD detection circuits is an attractive approach to solve transient or static latch-up issues, but incurs high area cost.
A need therefore exists for an improved ESD power clamp or I/O pad clamp that can be used as an electrical fast-transient whole-chip protection network. Such a device should be effective for application to maturing technology as such technology advances. An additional needed benefit would be a cost reduction of saved chip area.